This invention is in the field of voltage and current reference circuits as used in integrated circuits. Embodiments are directed to curvature compensation in reference circuits of the bandgap reference type.
The powerful computational and operation functionality provided by modern integrated circuits has enabled the more widespread distribution of computing power in larger-scale systems. One example of such distributed electronic functionality is the so-called “Internet of Things” (IoT) contemplates the widespread deployment of electronic devices as sensors and controllers, with networked communications among those devices. Modern smartphones and wearables also deploy computational and operational functionality into a large number of distributed nodes; implantable medical devices constitute another type of distributed functionality. Many of these applications necessitate the use of batteries or energy scavenging devices to power the integrated circuits. As such, many modern integrated circuits are called upon to be “power-aware”, designed to consume minimal power during operation and standby.
Voltage and current reference circuits are important functions in a wide range of modern analog, digital, and mixed-signal integrated circuits, in order to optimize the performance of such circuits as operational amplifiers, comparators, analog-to-digital and digital-to-analog converters, oscillators, phase-locked loops and other clock circuits, and the like. This optimization is especially important for power-aware applications in which power consumption can be a dominating factor in circuit and system design. As well known in the art, voltage and current reference circuits ideally generate their reference levels in a manner that are stable over variations in process parameters, power supply voltage levels, and operating temperature.
FIG. 1 illustrates “bandgap” reference circuit 10, constructed in the conventional manner. In this example, p-channel metal-oxide-semiconductor (PMOS) transistor 6p, with its source at the Vdd power supply voltage, serves as a current source to two bipolar transistor branches to which its drain is connected through resistor 7. One branch is formed by resistor 9a connected between resistor 7 and the emitter of p-n-p transistor 8a, while the other branch is formed by resistor 9b connected between resistor 7 and resistor 11, which in turn is connected to the emitter of p-n-p transistor 8b. Typically, transistor 8b will have an emitter area that is some multiple N:1 of the emitter area of transistor 8a, so that the currents conducted by the two transistors are similarly ratioed. The bases and collectors of transistors 8a, 8b are connected to the Vss reference level. This construction of reference circuit 10 is common in complementary metal-oxide-semiconductor (CMOS) integrated circuits, as bipolar p-n-p transistors 8a, 8b are typically present as parasitic devices in the CMOS structure. In this conventional arrangement, the emitter of transistor 8a is connected to one input of amplifier 15, while the other input of amplifier 15 is connected to the node between resistors 9b and 11. The output AMPOUT of amplifier 15 is connected to the gate of transistor 6p. 
According to this construction, the output voltage AMPOUT from amplifier 15 is based on one parameter that varies in a manner complementary to absolute temperature (CTAT) combined with another parameter that varies proportionally with temperature (PTAT). The CTAT parameter in this circuit is the base-emitter voltage of transistor 8a, and the PTAT parameter is the difference in the base-emitter voltages of transistors 8a, 8b, which is reflected as the voltage drop across resistor 11. The sum of these two voltages is thus constant over variations in temperature, at least to a first approximation, and appears at the drain of transistor 6p as output voltage VBG. This output voltage VBG is typically at about the bandgap voltage of the semiconductor (e.g., 1.2 volts for silicon), and as such reference circuit 10 is thus commonly referred to in the art as a “bandgap reference circuit”. Additional transistors (not shown) are typically mirrored with PMOS transistor 6p to establish and provide output currents that are similarly stable over variations in temperature. Reference circuit 10 can be made “self-biased” by biasing amplifier 15 with a copy of the current conducted by transistor 6p, in which case the circuit will be relatively insensitive to variations in the Vdd power supply voltage.
However, the base-emitter voltages of bipolar transistors 8a, 8b are not exactly linear over temperature because of non-linear temperature behavior in the bipolar junction transistor (BJT) saturation current. The combination of the CTAT base-emitter voltage with the PTAT difference in base-emitter voltages is thus often insufficient to attain the desired temperature stability of the reference voltage. This variation of base-emitter voltage (Vbe) over temperature is generally referred to as the “curvature” of Vbe, referring to the curve in the Vbe vs. temperature characteristic from the linearly CTAT ideal.
FIG. 2 illustrates a simplified schematic of reference circuit 10′ including curvature compensation according to one conventional technique. Reference circuit 10′ is constructed similarly as reference circuit 10 described above in connection with FIG. 1, but with n-channel MOS (NMOS) transistor 6n in place of PMOS transistor 6p. In this conventional reference circuit 10′, curvature compensation is provided by resistor 13, which is formed in an n-type well in the integrated circuit; in contrast, resistors 9a, 9b, 11 are typically formed in polycrystalline silicon. Because of its formation in an n-well, resistor 13 will exhibit a non-linear temperature coefficient, and thus the collector currents will develop a non-linear voltage across resistor 13. The non-linearity of this voltage drop across resistor 13 tends to compensate for the non-linearity of Vbe over temperature. While this curvature compensation is relatively easy to design and implement, without requiring significant modifications to existing circuits, the n-well realization of resistor 13 introduces additional process sensitivity, specifically sensitivity to variations in n-well sheet resistance, which is a difficult parameter to control over typical process windows. This approach to curvature compensation is thus typically less robust than required for good yield and performance.
Another conventional approach for curvature compensation involves the introduction of a non-linear bias current to cancel out the non-linearity of Vbe over temperature. Filanovsky et al., “BiCMOS Cascaded Bandgap Voltage Reference”, IEEE 39th Midwest symposium on Circuits and Systems, Vol. 2 (IEEE, 1996), pp.943-946describes this approach as carried out by a translinear current polynomial circuit to produce a current that is PTAT to the third degree (i.e., proportional to T3), and a current that is PTAT to the fourth degree. These currents are added with the collector current in the reference circuit to compensate for non-linearities. However, this approach necessitates the formation of cascaded bipolar transistors, and thus not conducive to implementation in CMOS technologies (in which the collectors of parasitic bipolar devices are all connected to the substrate).
Another approach to curvature compensation is described in U.S. Pat. No. 6,255,807, incorporated herein by reference. According to this technique, an additional amplifier gain stage is added to the reference circuit, and adds non-linearity into the feedback loop. While this technique provides good curvature compensation, the additional amplifier stage requires significant chip area to implement, and consumes additional power that renders it less than optimal for power-aware applications.
By way of further background, U.S. Pat. No. 9,104,217, issued Aug. 11, 2015, commonly assigned herewith and incorporated herein by reference, describes a reference circuit with curvature compensation implemented by way of a translinear circuit that draws a non-linear current from the bipolar collector currents, and that can be realized by MOS transistors.